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Dr. C. Pakkiraiah View All

Assistant Professor

School of Technology

Dr. C. Pakkiraiah did his Ph.D in the faculty of Electronics and Communication Engineering from Sri Venkateswara University, Tirupathi, AP. He has also obtained additional qualifications UGC-JRF, GATE, and UGC-Assistant Professor. He has over seven years of teaching experience. He has supervised over eight students’ projects at UG and PG Levels. He has served in various administration roles such as a member of R &D, NAAC, NBA and BoS in his previous employment. He is a member of American Chamber of Research. He has published ten articles in International and National Journals, and Conferences. He was a reviewer of International Journal of Computing and Digital Systems (Scopus).

    • Graduation In :

      Electronics and Communication Engineering

    • Graduation From :

      SITAMS-JNTUA

    • Graduation Year :

      2009

    • Post Graduation In :

      VLSI

    • Post Graduation From :

      SVEC-JNTUA

    • Post Graduation Year :

      2013

    • Doctorate In :

      Electronics and Communication Engineering (VLSI)

    • Doctorate From :

      S.V.University, Tirupati

    • Doctorate Year :

      2024

    • 6 Years 10 Months

  • Publications in Journals

    • C Pakkiraiah and RVS Satyanarayana. Design and FPGA realization of energy efficient reversible full adder for digital computing applications. Journal of VLSI circuits and systems, volume 6, pages 7–18, 2024. [Scopus Indexed Journal].
    • Ch Pakkiraiah and Dr RVS Satyanarayana. An innovative design of low power binary adder based on switching activity. International Journal of Computing and Digital Systems, volume 11, pages 861–871. University of Bahrain, 2022. [Scopus Indexed Journal].
    • C Pakkiraiah and RVS Satyanarayana. Design of low power full adder using multilayer perceptron to minimize energy delay product of computational logic circuits. IUP Journal of Electrical and Electronics Engineering, volume 15, pages 42–58. IUP Publications, 2022.
    • C Pakkiraiah and RVS Satyanarayana. Design of low power artificial hybrid adder using neural network classifiers to minimize energy delay product for arithmetic application. Int. J. Comput. Appl, volume 184, pages 1–8, 2022.
    • C Pakkiraiah and R Satyanarayana. FPGA realization of low power multi-layer perceptron full adder to minimize edp of modular multiplier. Int. J. Electron. Eng. Appl, volume 10, pages 01–12, 2022.
    • SREENIVASULU PASUPULETI and C PAKKIRAIAH. Design of novel 4-bit multiplier circuit by using self resetting modified gdi logic (sr-mgdil). 2017.
    • Pakkiraiah Chakali and Madhu Kumar Patnala. Design of high speed ladner-fischer based carry select adder. International Journal of Soft Computing and Engineering (IJSCE), volume 3, pages 173–176, 2013.
    • Pakkiraiah Chakali and Madhu Kumar Patnala. Design of high speed kogge-stone based carry select adder. International Journal of Emerging Science and Engineering (IJESE), volume 1, pages 2319–6378. Citeseer, 2013.
    • Pakkiraiah Chakali, Adilakshmi Siliveru, and Neelima Koppala. Design of high speed six transistor full adder using a novel two transistor xor gates. International Journal of Advanced Research in Computer Science and Electronics Engineering (IJARCSEE), volume 1, 2012.
    • Pakkiraiah Chakali et al. A novel low power and area efficient carry look
      ahead adder using gdi technique.
    • International Journal of Advanced
      Research in Computer Engineering and Technology, volume 1, pages 221–
      227, 2012.

    Publications in Conferences

    • Ch Pakkiraiah and RVS Satyanarayana. Design and fpga realization of an energy efficient artificial neural modular exponentiation architecture. In International Conference on Computing, Communication and Learning, pages 115–126. Springer, 2022. [Scopus Indexed-NIT, Surat]
    • C Pakkiraiah and RVS Satyanarayana. Design of low power modular (x mod p) reduction unitbased on switching activity for data security applications. In Advances in VLSI and Embedded Systems: Select Proceedings of AVES 2021, pages 13–25. Springer, 2022. [Scopus Indexed-NIT Warangal]
    • Received Best Researcher Award of International Congress for Research Excellence for article An Innovative Design of Low Power Binary Adder based on Switching Activity.
    • Received Gold Medal for having secured First Rank in Master of Technology in VLSI.
    • Qualified in GATE in the year 2011, 2013, 2014, and 2017 with a score in between 300-400.